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Texas Instruments SN74AUP1G80 D-Type Flip-Flop

Texas Instruments SN74AUP1G80 D-Type Flip-Flop is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The Texas Instruments SN74AUP1G80 is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This circuitry inhibits current backflow into the device, which prevents damage to the device.

Features

  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • ESD performance tested per JESD 22
    • 2000V human-body model (A114-B, Class II)
    • 1000V charged-device model (C101)
  • Available in the Texas Instruments NanoStar™ package
  • Low static-power consumption (ICC = 0.9µA maximum)
  • Low dynamic-power consumption (Cpd = 4.3pF typical at 3.3V)
  • Low input capacitance (Ci = 1.5pF typical)
  • Low noise – overshoot and undershoot <10% of VCC
  • Ioff supports partial-power-down mode operation
  • Schmitt-trigger action allows slow input transition and better switching noise immunity at the input (Vhys = 250mV typical at 3.3V)
  • Wide operating VCC range of 0.8V to 3.6V
  • Optimized for 3.3V operation
  • 3.6V I/O tolerant to support mixed-mode signal operation
  • tpd = 4.4ns maximum at 3.3V
  • Suitable for point-to-point applications

Applications

  • Home automation
  • Factory automation
  • Test and measurement
  • Enterprise switching
  • Telecom infrastructure
  • Personal electronics
  • White goods

Functional Block Diagram

Block Diagram - Texas Instruments SN74AUP1G80 D-Type Flip-Flop

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Published: 2018-04-20 | Updated: 2025-02-21