Altera / Intel Cyclone® IV FPGAs

Altera / Intel® Cyclone® IV FPGAs extend the Cyclone® FPGA series leadership in providing the market's lowest cost, lowest power FPGAs, now with a transceiver variant. Cyclone® IV devices are targeted to high volume, cost-sensitive applications, enabling system designers to meet increasing bandwidth requirements while lowering costs. Providing power and cost savings, without sacrificing performance, along with a low-cost integrated transceiver option, Cyclone® IV devices are ideal for low-cost, small-form-factor applications in the wireless, wireline, broadcast, industrial, consumer, and communications industries.

Built on an optimized low-power process, the Altera / Intel® Cyclone IV device family offers two variants. Cyclone® IV E offers low power, high functionality, and low cost.

Cyclone® IV GX devices offer an on-chip transceiver with an I/Os speed up to 3.125Gbps. This high-speed transceiver supports many serial I/O protocols, such as Gigabit Ethernet (GbE), PCI Express (PCIe), CPRI, XAUI, 3G Triple-Rate SDI, Serial RapidIO®, SATA, DisplayPort, and V-by-One, that are migrating from the cutting edge to the mainstream. Cyclone® IV GX FPGAs also include an embedded PCIe hard IP block that, when utilized by the design engineer, does not use any of the FPGA logic and supports more functionality than many other competing FPGA architectures.

Features

Common Features:
Two variants:
- Cyclone® IV GX FPGAs with integrated 3.125Gbps transceiver I/Os for high-bandwidth applications
- Cyclone® IV E FPGAs for a wide spectrum of general logic, control plane, and other embedded control applications
Low-cost, low-power FPGA fabric:
- 6K to 150K logic elements
- Up to 6.3Mb of embedded memory
- Up to 360 18 × 18 multipliers for DSP processing intensive applications
Up to 535 user I/Os
Up to eight phase-locked loops (PLLs) per device
Offered in commercial and industrial temperature grades

GX Features:
Up to eight high-speed transceivers that provide:
- Data rates up to 3.125 Gbps
- 8B/10B encoder/decoder
- 8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer (PCS) interface
Dedicated hard IP for PCI Express (PIPE) (PCIe) Gen 1:
- ×1, ×2, and ×4 lane configurations
- End-point and root-port configurations
- Up to 256-byte payload
Wide range of protocol support:
- PCIe (PIPE) Gen 1 ×1, ×2, and ×4 (2.5Gbps)
- Gigabit Ethernet (1.25Gbps)
- CPRI (up to 3.072Gbps)