Digitally Addressable Lighting Interface
By Shaima Husain,
Microchip Technology Inc
Featured Products
Resources
The Digitally Addressable Lighting Interface (DALI) has emerged as a standard in Europe to address growing power issues, mostly for commercial and industrial purposes. DALI is part of the IEC 60929 specification, and relates specifically to digitally controlled dimmable fluorescent ballasts. DALI type ballasts can run at lower power levels than standard magnetic ballasts. Commercial development of DALI started around 1998. DALI consists of a two-wire serial bus and requires a special DALI power supply. The Master sends 16-bit Manchester encoded data packets, and the ballasts can respond with an 8-bit Manchester encoded data packet. Multi-Masters are allowed, and two Masters can share the same ballast. There are 64 channels, or individual addresses, available for the ballasts to be connected to one interface line. Each DALI bus can have 16 groups at the maximum, and there are 16 scenes available. There is no error checking in the DALI protocol. This application note describes the basic communication between the control device and the control gear, which includes explanation of electrical specifications, timing, packet formats and Manchester encoding/decoding.
Terminology
Control Gear: Ballast or Sensor/Receiver
Control Device: Controller/Transmitter
Forward Frame: Packet sent from the control device to the control gear
Backward Frame: Response packet sent from the control gear to the control device
Short Address: Address of an individual control gear in the system
Group Address: Address to a group of control gear
Broadcast: Address used to address all the control gears at once
Direct Arc Power: Power level sent to an individual ballast or sent as a broadcast to all control gear, to immediately set the lamps to that power
Physical Layer
Topology
Unlike analog systems, DALI does not require any hard- wired power circuit control groups. The combination of individual ballast addressing with digital switching eliminates vertical switch wiring. DALI has a free-form layout ( Figure 1 ). Daisy chain, star topology and multi- drop are all allowed. A combination of two or more topologies is also allowed.
Figure 1: DALI free-form layout
Electrical Specifications
The physical low level or active state for DALI has been defined with the interface voltage of < 9.5V. The high- level condition, or DALI idle, is an interface voltage between 9.5V to 22.5V, most common being 16V. Maximum system current is limited to 250 mA. Response time of the current limiter circuit is < 10 μs. Each component connected to the interface may consume a maximum of 2 mA. Connectors are non- polarized at the receiver. DALI is usually optically isolated from the microcontroller and has a data transfer rate of 1200 bits per second.
Figure 2: DALI electrical specifications
Connectors
There are no specific connectors dedicated for the DALI interface. Two-wire connectors with common screw terminals or push fit suffice(Figure 3).
Figure 3: Two-Wire connectors
Cabling
Due to the transmission rate, there is no need for spe- cial cables or wires. Two-wire standard electrical cables can get the job done. 18 AWG, class 1 or 2 cables (solid or stranded) are commonly used on many fixtures. They are often purple in color and usually rated 600V. A maximum voltage drop of up to 2V is allowed across the connecting wires from the interface supply to each system component. The maximum distance between two communicating units should be 300 meters (984 feet).
DALI Circuits
There is no specification or recommendations on how to implement the circuit design for DALI. The following optically isolated circuit interfaces a PIC16F1947 to the DALI bus.
Figure 4: Isolated communications circuit
Figure 5: Isolated communications circuit diagram
DALI Power Supply Circuits
DALI power supply needs fast response time and efficient current limiting. This simple circuit works well.
Figure 6: Cicuit
DALI Transmission
DALI uses Manchester (bi-phase) encoding to send the Start bit and the information bits. The information rate is 1200 bps with an acceptable range of ± 10%. One bit time is 833.33 μs. The Most Significant bit (MSb) is sent out first (Figure 7)
Figure 7: DALI Transmission
Forward Frame (control device –› control gear)
Forward frame is the packet sent by the control device to the control gear. It consists of one Start bit, eight address bits, eight data bits and two Stop bits. The bits are sent MSb first.
Figure 8: Forward frame
Backward Frame (control gear –› control device)
Backward frame is the response packet sent by the control gear back to the control device. It consists of one Start bit, eight data bits and two Stop bits. The bits are sent MSb first.
Figure 9: Backward frame
Backward frame data byte: In a response frame (Backward frame) ‘0xFF’ is considered a ‘Yes’. If a response is expected and the line stays Idle, response is considered a ‘No’ from the control gear. Other values vary depending on the command the control gear is responding to.
Timing
As mentioned previously, the bit transfer rate for DALI is 1200 bits per second with room for an error of ±10%. ‘Te’ is used to indicate half-bit time, which is 416.67 μs. A forward packet lasts for 38 Te, which is equal to 15.83 ms. A backward frame takes 22 Te or 9.17 msec. The time between two consecutive forward frames is at least 22 Te. The time between forward frame and back- ward frame is greater than or equal to 7 Te, and less than or equal to 22 Te. The time between backward frame and forward frame is at least 22 Te.
Figure 10: Frame timing
Manchester Encoding/Decoding
Any packet sent between the control device and control gear is a bi-phase Manchester encoded packet. The packet is then decoded, and the address and messages are then processed accordingly. Our lighting communication board has a PIC16F1947 microcon- troller unit along with an isolated DALI communication circuit interface and a simple power supply. Please see “Appendix A” for the schematic details.
Since the signal from the DALI bus is inverted by the opto-coupler, the following explanation is how the PIC ® microcontroller views the Manchester encoding/decoding.
The Manchester code is a digital encoding format in which symbol ‘ 1 ’ is represented by a falling edge (high followed by low), and symbol ‘ 0 ’ is represented by a rising edge (low followed by high). Both the high and low pulses have equal width, which is equal to half the bit period.
Figure 11: Manchester encoding of a bit
Manchester Encoding
The outgoing message is encoded using Timer1, and the packet is sent out using the RC5 pin. An interrupt is generated using Timer1 every Te, which is 416.67 μs. Te is the half-bit time, and this is where we want to change the phase of the signal. If we were sending out a ‘ 1 ’ as our bit, the first half is ‘ 1 ’ and at the interrupt the signal is reversed and vice versa. As a result, the out- put is a Manchester encoded packet, ready to be decoded by the control gear if sent by the control device, or decoded by the control device if sent as a response by the control gear back to the control device.
Figure 12: Manchester encoding
Sample Code
Example 1:
void TransmitFrame(void)
{
static uint8_t bitcount = 0;
if (TxFlag.TransmitMode && TE_TMR_INT_ENABLE)
{
switch (makeframe)
{
case start:
......................................
......................................
break;
case alldata:
if (TxFlag.Secondhalf)
{
DATA_OUT ^= 1;
TxFlag.Secondhalf = CLEAR;
bitcount++;
if (bitcount > 15)
{
makeframe=stop;
bitcount = 0;
}
}
else
{
if (FwdFrame.Word & 0x8000) DATA_OUT = DALI_LO;
else DATA_OUT=DALI_HI;
FwdFrame.Word <<= 1;
TxFlag.Secondhalf = SET;
makeframe=alldata;
}
break;
case stop:
..........................................
..........................................
break;
..........................................
..........................................
}
}
}
Manchester Decoding
Manchester decoding is more complicated than Manchester encoding. As the reception starts, the receiver, whether it be the control gear or the control device, makes sure the packet is received in its entirety starting with the Start bit, then an 8- or 16-bit message and, finally, at least two idles to indicate the Stop bit. The decoding is done using the external interrupt pin RB0 on the PIC16F1947. This pin is specially used to generate an interrupt every time the phase of the incoming signal changes. Timer1 is used to generate interrupt every 3/4 th of the bit, so the value is measured at that point, and that decides whether the bit is a ‘ 0 ’ or a ‘ 1 ’. Timer1 is reset and reloaded in the middle of the bit when the external interrupt happens, and that keeps the error due to drifting in check.
Figure 13: Manchester decoding
Sample Code
Example 2:
void ReceiveFrame(void)
{
static uint16_t count = 0;
static uint16_t HalfBitTime=0;
static uint16_t LoadHalfBitTime=0;
if (RxFlag.ReceiveMode)
{
switch (makeframe)
{
case start:
............................
............................
break;
case address:
if (count <= 7)
{
if (TE_TMR_INT_ENABLE && TE_TMR_INT_FLAG)
{
TE_TMR_INT_FLAG = CLEAR;
TE_TMR_ON=CLEAR;
receivebuff <<= 1;
if (DATA_IN_INT== DALI_LO)
{
SET_INT_FALLING_EDGE();
receivebuff |= 0x01;
}
else SET_INT_RISING_EDGE();
TE_TMR_INT_ENABLE = CLEAR;
TE_TMR_ON = CLEAR;
EDGE_INT_ENABLE= SET;
}
else if (EDGE_INT_ENABLE)
{
EDGE_INT_ENABLE = CLEAR;
TE_TMR_INT_ENABLE = SET;
TE_TMR_VALUE = TMRLoadVal;
TE_TMR_ON = SET;
count++;
}
else
{
RxFlag.Error = SET;
RxFlag.ListenMode = SET;
break;
}
if (count <= 7)
makeframe = address;
else
{
count = 0;
makeframe = data;
EDGE_INT_ENABLE = CLEAR;
EDGE_INT_FLAG = CLEAR;
TE_TMR_INT_ENABLE = SET;
TE_TMR_VALUE = TMRLoadVal;
TE_TMR_ON = SET;
FwdFrame.Byte.Address = receivebuff;
receivebuff = CLEAR;
}
}
break;
.............................................
.............................................
}
}
}
Conclusion
The DALI circuit with simple power supply and Manchester encoded/decoded communication imple- mented using PIC16F1947 along with the ‘C’ code, provides a solid foundation for implementing DALI commissioning and commands for both the control device, as well as the control gear.
APPENDIX A
Figure 14: DALI schematics