Analog Devices Inc. AD9684 14-Bit 500MSPS Dual ADCs
Analog Devices AD9684 14-Bit, 500MSPS LVDS, Dual Analog-to-Digital Converters (ADC) feature an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease-of-use. AD9684 ADCs provide a high sampling rate for wide bandwidth analog signals, excellent linearity, and low power in a small 12mm × 12mm, 196-ball ball grid array (BGA) package. Optimized for wide input bandwidth, AD9684 supports intermediate frequency (IF) sampling of signals up to 2GHz. The programmable threshold detector monitors incoming signal power using the fast detect output bits of the ADC. Because this threshold indicator has low latency, the designer can quickly reduce the system gain to avoid an over-range condition at the ADC input.
The dual ADC output data is routed directly to the external 14-bit LVDS output port that supports double data rate (DDR) formatting. The SYNC± input pins support multiple device synchronization. In addition, the AD9684 offers flexible power-down options for significant power savings. Designers can program all of the AD9684 features using a 1.8V to 3.4V capable 3-wire serial port interface (SPI). Specified to operate over the −40°C to +85°C industrial temperature range, AD9684 ADCs are well-suited for communications, diversity multiband, multimode digital receivers, 3G/4G, TD-SCDMA, W-CDMA, MC-GSM, LTE, general-purpose software radios, ultrawideband satellite receiver, instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions), radar, digital oscilloscopes, high-speed data acquisition systems, DOCSIS CMTS upstream receiver paths, and HFC digital reverse path receivers.
Features
- Parallel LVDS (DDR) outputs
- 1.1W total power per channel at 500MSPS (default settings)
- SFDR = 85dBFS at 170MHz fIN (500MSPS)
- SNR = 68.6dBFS at 170MHz fIN (500MSPS)
- ENOB = 10.9 bits at 170MHz fIN
- DNL = ±0.5LSB
- INL = ±2.5LSB
- Noise density = −153dBFS/Hz at 500MSPS
- 1.25V, 2.50V, and 3.3V supply operation
- No missing codes
- Internal analog-to-digital converter (ADC) voltage reference
- Flexible input range and termination impedance:
- 1.46Vp-p to 2.06Vp-p (2.06Vp-p nominal)
- 400Ω, 200Ω, 100Ω, and 50Ω differential
- SYNC± input allows multichip synchronization
- DDR LVDS (ANSI-644 levels) outputs
- 2GHz usable analog input full power bandwidth
- >96dB channel isolation/crosstalk
- Amplitude detect bits for efficient AGC implementation
- Two integrated wideband digital processors per channel
- 12-bit Numerically Controlled Oscillator (NCO)
- 3 cascaded half-band filters
- Differential clock inputs
- Serial port control
- Integer clock divide by 2, 4, or 8
- Small signal dither
Applications
- Communications
- Diversity multiband, multimode digital receivers
- 3G/4G, TD-SCDMA, W-CDMA, MC-GSM, LTE
- General-purpose software radios
- Ultrawideband satellite receiver
- Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions)
- Radar
- Digital oscilloscopes
- High-speed data acquisition systems
- DOCSIS CMTS upstream receiver paths
- HFC digital reverse path receivers
Functional Block Diagram
Related Products
Analog Devices Inc. High-Speed Converters
A large portfolio of high-speed digital-to-analog converter products.